module top (
    input               clk,
    input               rst,
	input  wire [31:0] 	data_in,
	output reg  [ 5:0]  pos_out_reg	
);
wire [ 5:0] pos_out;
	Vector inst_Vector (.data_in(data_in), .pos_out(pos_out));
always@(posedge clk)
    if(rst)
        pos_out_reg <= 6'b0;
    else 
        pos_out_reg <= pos_out;

endmodule
